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Preliminary Technical Data
FEATURES
600 mA/1000 mA, 2.5 MHz Buck-Boost DC-to-DC Converter ADP2503/ADP2504
GENERAL DESCRIPTION
The ADP2503/ADP2504 are high efficiency, low quiescent current step-up/step-down dc-to-dc converters that can operate at input voltages above, below, or equal to the regulated output voltage. The power switches and synchronous rectifiers are internal to minimize external part count. At high load currents, the ADP2503/ADP2504 use a current-mode, fixed frequency PWM control scheme for optimal stability and transient response. To ensure the longest battery life in portable applications, the ADP2503/ADP2504 have an optional power save mode that reduces the switching frequency under light load conditions. For wireless and other low noise applications where variable frequency power save mode may cause interference, the logic control input sync forces fixed frequency PWM operation under all load conditions. The ADP2503/ADP2504 can run from input voltages between 2.3 V and 5.5 V, allowing single lithium or lithium polymer cell, multiple alkaline or NiMH cells, PCMCIA, USB, and other standard power sources. The ADP2503/ADP2504 have fixed output options ranging from 2.8 V to 5 V. Compensation is internal to minimize the number of external components. During logic-controlled shutdown, the input is disconnected from the output and draws less than 1 A from the input source. Operating as a boost converter, the ADP2503/ADP2504 feature a true load disconnect function that isolates the load from the power source. Other key features include under voltage lockout to prevent deep battery discharge and soft start to prevent input current overshoot at startup.
1 mm height profile Compact PCB footprint Seamless transition between modes 38 A typical quiescent current 2.5 MHz operation enables 1 H inductor Input voltage: 2.3 V to 5.5 V Fixed output voltage: 2.8 V to 5.0 V 600 mA (ADP2503) and 1000 mA (ADP2504) output options Boost converter configuration with load disconnect Sync pin with three different modes: Power save mode (PSM) for improved light load efficiency Forced fixed frequency operation mode Synchronization with external clock Internal compensation Soft start Enable/shutdown logic input Overtemperature protection Short-circuit protection Undervoltage lockout protection Small 10-lead 3 mm x 3 mm LFCSP/QFN package
APPLICATIONS
Wireless handsets Digital cameras/portable audio players Miniature hard disk power supplies USB powered devices
TYPICAL APPLICATION CIRCUIT
1.0H
SW1 VIN 2.3V TO 5.5V
SW2
ADP2503
PVIN VIN VOUT FB
VOUT 2.8V TO 5V
10F
22F
SYNC
07475-001
EN ON OFF
AGND PGND
Figure 1. Application Circuit
Rev. PrB
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ADP2503/ADP2504 TABLE OF CONTENTS
Features .............................................................................................. 1

Preliminary Technical Data
Reverse Current Limit ............................................................... 10
Power save Mode........................................................................ 10
Soft Start ...................................................................................... 10
Enable........................................................................................... 11
Undervoltage Lockout ............................................................... 11
Thermal Shutdown .................................................................... 11
Short Circuit Protection ............................................................ 11
Applications Information .............................................................. 12
Inductor Selection ...................................................................... 12
PCB Layout Guidelines.................................................................. 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
Applications ....................................................................................... 1
General Description ......................................................................... 1
Typical Application Circuit ............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Description .............................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ...................................................................... 10
REVISION HISTORY
8/08--Revision PrB
Rev. PrB | Page 2 of 16
Preliminary Technical Data SPECIFICATIONS
ADP2503/ADP2504
VIN = 3.6 V, VOUT = 3.3 V, @ TA = TJ = -40C to +125C for minimum/maximum specifications and TA = +25C for typical specifications, unless otherwise noted.1 Table 1.
Parameters INPUT CHARACTERISTICS Input Voltage Range Undervoltage Lockout Threshold Undervoltage Lockout Threshold OUTPUT CHARACTERISTICS Output Voltage Range Feedback Voltage Feedback Impedance Output Voltage Initial Accuracy (PWM Mode, No Load) Load and Line Regulation CURRENT CHARACTERISTICS Quiescent Current (VIN) Shutdown Current SWITCH CHARACTERISTICS N-Channel Switches (LFCSP) P-Channel Switches (LFCSP) P-Channel Leakage Switch Current Limit ADP2504 ADP2503 Reverse Current Limit OSCILLATOR AND STARTUP Oscillator Frequency On Time PMOS1 (Buck Mode) On Time NMOS2 (Boost Mode) Sync Clock Frequency Sync Clock Minimum Off Time Soft Start Period LOGIC LEVEL CHARACTERISTICS EN, SYNC Input High Threshold EN, SYNC Input Low Threshold EN, SYNC Leakage Current THERMAL CHARACTERISTICS Thermal Shutdown Threshold Thermal Shutdown Hysteresis
1
Conditions
Min 2.3 2.2 2.13 2.8 0.495
Typ
Max 5.5 2.3 2.23 5.0 0.55 +2 0.5 0.6
Unit V V V V V k % % % A A m m A A A A MHz ns ns MHz ns s V V A C C
VIN rising VIN falling
2.25 2.18
0.5 450
ADP2503/ADP2504 (PWM operation, no load) VIN = 2.3 V to 3.6 V, ILOAD = 0mA to 500mA, forced PWM mode VIN = 2.3 V to 5.5 V, ILOAD = 0mA to 500mA, forced PWM mode IOUT = 0 mA, V mode = EN = VIN = 3.6 V, device not switching TA = TJ = -40C to +85C VIN = 3.6 V VIN = VOUT = 3.6 V TJ = -40C to +85C
-2
38 0.2 150 150
50 1
1 1.3 1.0 2.0 1.4 1.1 2.5 2.8 200 2.8 200 1.2 -1 +0.1 150 25 0.4 +1
VIN = 2.3 V to 5.5 V Minimum duty cycle = 30% Maximum duty cycle = 50% (x2)
2.2 130 2.2 160
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
Rev. PrB | Page 3 of 16
ADP2503/ADP2504 ABSOLUTE MAXIMUM RATINGS
Table 1.
Parameter PVIN, VIN, SW1, SW2, VOUT, SYNC, EN, FB PGND to AGND Operating Ambient Temperature Operating Junction Temperature Storage Temperature Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) ESD Human Body Model ESD Charged Device Model ESD Machine Model Rating -0.3 V to +6 V -0.3 V to 0.3 V -40C to +85C -40C to +125C -65C to +150C 300C 215C 220C 1000 V 500 V 100 V
Preliminary Technical Data
THERMAL RESISTANCE
JA is specified for device soldered JEDEC2S2P PCB. For a typical printed circuit board of a handset, the total thermal resistance is higher. For correct operation up to 85C ambient temperature the total thermal resistance must not exceed 100 K/W. Table 2.
Package Type 10-Lead LFCSP (QFN) JA 84 Unit C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to GND.
Rev. PrB | Page 4 of 16
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTION
VOUT 1 SW2 2 PGND 3 SW1 4 PVIN 5
ADP2503/ADP2504
ADP2503/ ADP2504
TOP VIEW (Not to scale)
10 FB 9 8 7 6 AGND VIN SYNC EN
07475-003
*CONNECT PADDLE TO GND.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 Mnemonic VOUT SW2 PGND SW1 PVIN EN SYNC Description The output of the ADP2503/ADP2504. Connect the output capacitor between VOUT and PGND. Power Switch 2 Connection. This is the internal connection to the input PMOS and NMOS switches. Connect SW2 to the inductor with a short, wide track. Power GND. Connect the input and output capacitors and PGND pin to a PGND plane. Power Switch 1 Connection. This is the internal connection to the output PMOS and NMOS switches. Connect SW1 to the inductor with a short, wide track. Power Input. This the input to the buck-boost power switches. Place a 10 F capacitor between PVIN and PGND as close as possible to the ADP2503/ADP2504. Enable. Drive EN high to turn on the ADP2503/ADP2504. Bring EN low to put the part into shutdown mode. The SYNC pin permits the ADP2503/ADP2504 to operate in three different modes. Normal operation: with SYNC driven low, the ADP2503/ADP2504 operates at 2.5 MHz PWM mode for heavy and medium loads, and moves to power save mode (PSM) mode for light loads. Forced PWM operation: with SYNC driven high, the ADP2503/ADP2504 operates at fixed 2.5 MHz PWM mode for all load conditions. SYNC mode: to synchronize the ADP2503/ADP2504 switching to an external signal, drive this pin with a clock between 2.2 MHz and 2.8 MHz. The SYNC signal must have on and off times greater than 160 ns. Analog Power Supply. This is the supply for the ADP2503/ADP2504 internal circuitry. Analog Ground. Output Feedback. This is an input to the internal error amplifier. Connect the paddle to PGND.
8 9 10 EP
VIN AGND FB Paddle
Rev. PrB | Page 5 of 16
ADP2503/ADP2504 TYPICAL PERFORMANCE CHARACTERISTICS
100 90 80 70
EFFICIENCY (%)
Preliminary Technical Data
100 90 80 70
EFFICIENCY (%)
60 50 40 30 20 10 0 0.001 0.01 IOUT (A)
VIN = 5.5V VIN = 4.2V VIN = 3.6V VIN = 2.3V
07475-103
60 50 40 30 20 10 VIN = 5.5V VIN = 4.2V VIN = 3.6V VIN = 2.3V 0.01 IOUT (A) 0.1 1
07475-108 07475-106 07475-105
0.1
1
0 0.001
Figure 3. Efficiency vs. Output Current, PWM Mode (VOUT = 5.0 V)
Figure 6. Efficiency vs. Output Current, PSM and PWM Mode (VOUT = 3.3 V)
100 90 80 70
EFFICIENCY (%)
100 90 80 70
EFFICIENCY (%)
60 50 40 30 20 10 0 0.001 0.01 IOUT (A) VIN = 5.5V VIN = 4.2V VIN = 3.6V VIN = 2.3V
07475-104
60 50 40 30 20 10 VIN = 5.5V VIN = 4.2V VIN = 3.6V VIN = 2.3V 0.01 IOUT (A) 0.1 1
0.1
1
0 0.001
Figure 4. Efficiency vs. Output Current, PSM and PWM Mode (VOUT = 5.0 V)
Figure 7. Efficiency vs. Output Current, PWM Mode (VOUT = 2.8 V)
100 90 80 70
EFFICIENCY (%) EFFICIENCY (%)
100 90 80 70 60 50 40 30 VIN = 5.5V VIN = 4.2V VIN = 3.6V VIN = 2.3V
07475-109
60 50 40 30 20 10 0 0.001 0.01 IOUT (A)
20 10 1 0 0.001 0.01 IOUT (A)
VIN = 5.5V VIN = 4.2V VIN = 3.6V VIN = 2.3V 0.1 1
0.1
Figure 5. Efficiency vs. Output Current, PWM Mode (VOUT = 3.3 V)
Figure 8. Efficiency vs. Output Current, PSM and PWM Mode (VOUT = 2.8 V)
Rev. PrB | Page 6 of 16
Preliminary Technical Data
100 90
QUIESCENT CURRENT (A)
ADP2503/ADP2504
50 45 40 35 30 25 20 15 10 5
07475-107
80 70
EFFICIENCY (%)
60 50 40 30 20 10 0 2.3 2.8 3.3 3.8 VIN (V) 4.3 4.8 5.3 IOUT = 500mA IOUT = 100mA IOUT = 10mA
0 2.3
2.7
3.1
3.5
3.9 VIN (V)
4.3
4.7
5.1
5.5
Figure 9. Efficiency vs. Input Voltage (VOUT = 3.3 V)
Figure 12. Quiescent Current vs. Input Voltage (VOUT = 3.3 V)
3.35
VIN
VIN = 3.0V TO 3.6V VOUT = 5.0V
3.33
SW1
VOUTA (V)
3.31
4
3.29
2 3
SW2
VOUT
3.27
07475-110
1
07475-005
3.25 0 0.1 0.2 0.3 0.4 0.5 IOUT (A) 0.6 0.7 0.8 0.9
1.0
CH1 50.0mV BW CH2 1.00V BW M40.0s A CH2 CH4 5.00V BW T 18.20% CH3 5.00V BW
3.40mV
Figure 10. Load Regulation (VIN = 3.6 V, VOUT = 3.3 V)
Figure 13. Line Transient, PWM Mode (VIN = 3.0 V to 3.6 V, VOUT = 5.0 V)
2.8
VIN
VIN = 3.0V TO 3.6V VOUT = 3.3V
2.7 -40C
FREQUENCY (MHz)
2.6 +25C 2.5
2 4
SW1
SW2
2.4
+85C
3
07475-112
2.2 2.3
2.7
3.1
3.5
3.9 VIN (V)
4.3
4.7
5.1
5.5
CH1 50.0mV BW CH2 1.00V BW M40.0s A CH2 CH3 5.00V BW CH4 5.00V BW T 18.20%
3.40V
Figure 11. Frequency vs. Input Voltage Over Temperature (VOUT = 3.3 V)
Figure 14. Line Transient, PWM Mode (VIN = 3.0 V to 3.6 V, VOUT = 3.3 V)
Rev. PrB | Page 7 of 16
07475-006
2.3
VOUT
1
07475-113
ADP2503/ADP2504
VIN VIN = 3.0V TO 3.6V VOUT = 2.8V
Preliminary Technical Data
SW1
SW1
4
4
2 3
SW2
2
IOUT
VOUT
VOUT
07475-007
VIN = 3.6V VOUT = 3.3V
07475-010
1
1
CH1 50.0mV BW CH4 1.00V BW M40.0s A CH2 CH3 5.00V BW CH4 5.00V BW T 18.20%
3.40mV
CH1 100mV BW CH2 500mA CH4 2.00V BW
M100s A CH2 T 45.40%
-115mA
Figure 15. Line Transient, PWM Mode (VIN = 3.0 V to 3.6 V, VOUT = 2.8 V)
Figure 18. Mode Change by Load Transients, Load Rise (VOUT = 3.3 V)
VIN = 3.6V VOUT = 3.3V VOUT
1
SW1
IOUT
2
4
IOUT
SW1
4
2
SW2
07475-008
VIN = 3.6V VOUT = 3.3V
07475-011
3
1
VOUT
CH1 100mV BW CH2 250mA M100s A CH2 CH3 5.00V BW CH4 5.00V BW T 25.80%
60.0mA
CH1 100mV BW CH2 500mA CH4 2.00V BW
M100s A CH2 T 45.40%
410mA
Figure 16. Load Transient (VIN = 3.6 V VOUT = 3.3 V, IOUT = 100 mA to 350 mA)
Figure 19. Mode Change by Load Transients, Load Fall (VOUT = 3.3 V)
VIN = 3.6V VOUT = 3.3V
1
SW2
3
VIN = 4.0V VOUT = 3.3V
VOUT IOUT
2
4
SW1
SW1
4
2
ISW
SW2
07475-111
VOUT
07475-012
1
3
CH1 100mV BW CH2 250mA M100s A CH2 CH3 5.00V BW CH4 5.00V BW T 23.00%
60.0mA
CH1 50.0mV BW CH2 250mA CH3 5.00V BW CH4 5.00V BW
M 400ns A CH3 T 50.00%
2.40V
Figure 17. Load Transient (VIN = 3.6 V VOUT = 3.3 V, IOUT = 10 mA to 300 mA)
Figure 20. Typical PWM Switching Waveform, Buck Operation (VOUT = 3.3 V)
Rev. PrB | Page 8 of 16
Preliminary Technical Data
SW2
3
ADP2503/ADP2504
VIN = 3.0V VOUT = 3.3V SW1
4
SW1
4
VOUT = 3.3V VOUT
1
ISW
2
ISW
2
EN VOUT
07475-013 07475-018
1
3
CH1 20.0mV BW CH2 250mA CH3 5.00V BW CH4 5.00V BW
M 400ns A CH4 T 50.80%
2.40V
CH1 2.00V BW CH2 500mA BW M 100s A CH3 T 9.400% CH3 5.00V BW CH4 5.00V BW
2.40V
Figure 21. Typical PWM Switching Waveform, Boost Operation (VOUT = 3.3 V)
Figure 24. Startup into PWM Mode (VOUT = 3.3 V, IOUT = 300 mA)
SW2
3
VIN = 3.0V
VOUT = 3.3V
SW1
4
SW1 VOUT
4 1
VOUT = 3.3V
ISW
2
ISW
2
EN VOUT
07475-027 07475-019
1
3
CH1 20.0mV BW CH2 250mA CH3 5.00V BW CH4 5.00V BW
M 400ns A CH4 T 50.00%
2.40V
CH1 2.00V BW CH2 500mA BW M 100s A CH3 T 9.400% CH3 5.00V BW CH4 5.00V BW
2.40V
Figure 22. Typical PWM Switching Waveform, Buck-Boost Operation (VOUT = 3.3 V)
Figure 25. Startup into PWM Mode (VOUT = 3.3 V, IOUT = 10 mA)
VIN = 3.0V
VOUT = 3.3V
SW2
3
SW1
4
SW1
4
1
VOUT
VOUT = 3.3V
ISW ISW
2 2
EN
VOUT
07475-015 07475-023
1
3
CH1 100mV BW CH2 1.00A CH3 5.00V BW CH4 5.00V BW
M 4.00s A CH2 T 15.20%
820mA
CH1 2.00V BW CH2 500mA BW M 100s A CH3 T 9.400% CH3 5.00V BW CH4 5.00V BW
2.40V
Figure 23. Typical PSM Switching Waveform, Buck-Boost Operation (VOUT = 3.3 V)
Figure 26. Startup into PSM Mode (VOUT = 3.3 V, IOUT = 10 mA)
Rev. PrB | Page 9 of 16
ADP2503/ADP2504 THEORY OF OPERATION
1.0H SW1
4 2
Preliminary Technical Data
SW2
VIN
8
ADP2503/ADP2504
ADP2503/ADP2504 BIASING
VBAT = 2.3V TO 5.5V 10F
PVIN
5
PMOS1 NMOS1 2.25V NMOS2
PMOS2
VOUT
1
22F SOFT START
UVLO FB BAND GAP REFERENCE EN
6
THERMAL PROTECTION PWM CONTROL
10
-0.5V CS
EN
7
SYNC PGND
3 9
OSCILLATOR AGND
07475-025
Figure 27. ADP2503/ADP2504 Block Diagram
The ADP2503/ADP2504 are synchronous average currentmode switching buck-boost regulators designed to maintain a fixed output voltage VOUT from an input supply VIN that can be above, equal to, or below VOUT. When VIN is significantly greater than VOUT, the device is in buck mode: PMOS2 is always active, NMOS2 is always off and the switches PMOS1, NMOS1 consti tute a buck converter. When VIN is significantly lower than VOUT, the device is in boost mode: PMOS1 is always active, NMOS1 is always off and the switches NMOS2, PMOS2 constitute a boost converter. When VIN is in the range [VOUT - 10%; VOUT + 10%], the ADP2503/ADP2504 automatically enter the buck-boost mode. In buck-boost mode, the two operations buck (PMOS1 and NMOS1 switching in antiphase) and boost (NMOS2 and PMOS2 switching in antiphase) take place at each period of the clock. This is aimed at maintaining the regulation and keeping a minimal current ripple in the inductor to guarantee good transient performances.
POWER SAVE MODE
When the SYNC pin is low, the ADP2503/ADP2504 can operate in power save mode (PSM). In this mode, when the load current becomes lower than 75 mA nominally at VIN = 3.6 V, the controller pulls up VOUT and then halts the switching regime until VOUT goes back to a restart value. Then VOUT is pulled up again for a new cycle. This minimizes the switching losses at light load. When the load rises above 150 mA, the ADP2503/ADP2504 revert back to fixed PWM mode. This results in about 75 mA of hysteresis between PSM and fixed PWM, preventing oscillations between these two modes.
SOFT START
When the ADP2503/ADP2504 are started, VOUT is ramped from 0 V to its final programmed value in 200 s (typ). This limits the inrush current to less than 600 mA for a nominal output capacitor of 20 F. Because the VOUT start-up slope is constant, the inrush current becomes larger if the output capacitor is made larger.
REVERSE CURRENT LIMIT
In case of a short circuit on VOUT to a value greater than expected, the inductor current becomes negative (reverse current). The negative peak value is limited to 1.1 A by deactivating the switch PMOS2.
Rev. PrB | Page 10 of 16
Preliminary Technical Data
ENABLE
The device starts operation with soft start when the EN pin is brought high. Pulling the EN pin low forces the device into shutdown, with a typical shutdown current of 0.2 A. In this mode, the PMOS power switches are turned off, the NMOS power switches are turned on, and the control circuitry is not enabled. For proper operation, the EN pin must be terminated and must not be left floating.
ADP2503/ADP2504
THERMAL SHUTDOWN
When the junction temperature, TJ, exceeds 150C typical, the device goes into thermal shutdown. In this mode, the power switches are turned off. The device resumes operation when the junction temperature again falls below 125C typical.
SHORT CIRCUIT PROTECTION
When the nominal inductor peak current value of 1.5 A is reached, the ADP2503/ADP2504 first switch off the NMOS2 transistor if it was active. If the current thereafter continues to increase by an extra amount of 200 mA, the PMOS1 transistor is also switched off. This operation is reversible when the short circuit stops. It allows the inductor current ripple to be mini mized close to 1.5 A and, thus, the controller to restore VOUT even if a high load current is maintained after the short circuit.
UNDERVOLTAGE LOCKOUT
The undervoltage lockout circuit prevents the device from oper ating incorrectly at low input voltages. It prevents the converter from turning on the power switches under undefined conditions and therefore, prevents deep discharge of the battery supply. VIN must be greater than 2.25 V to enable the converter. During operation, if VIN drops below 2.18 V, the ADP2503/ADP2504 are disabled until the supply exceeds the UVLO rising threshold.
Rev. PrB | Page 11 of 16
ADP2503/ADP2504 APPLICATIONS INFORMATION
INDUCTOR SELECTION
The high 2.5 MHz switching frequency of the ADP2503/ ADP2504 allows for minimal output voltage ripple, while minimizing inductor size and cost. Careful inductor selection also optimizes efficiency and reduces electromagnetic interfe rence (EMI). The selection of the inductor value determines the inductor current ripple and loop dynamics.
Preliminary Technical Data
Table 4. Sample of Recommended Inductors
Value (H) 1.2 1.5 1 1 1.5 1.0 1.5 1.0 1.5 DCR (m) 55 60 100 55 70 90 120 85 120 ISAT (A) 1.7 1.5 1.8 1.6 1.5 1.5 1.2 1.7 1.3 Dimensions L xW x H (mm) 2.8 x 2.8 x 1.0 2.8 x 2.8 x 1.0 2.5 x 2 x 1.2 2.5 x 2 x 1 2.5 x 2 x 1 2.5 x 1.5 x 1.2 2.5 x 1.5 x 1.2 3.0 x 3.0 x 0.9 3.0 x 3.0 x 0.9
I L , peak (Buck) =
VOUT x (VIN - VOUT ) VIN x f OSC x L (VOUT - V IN ) VOUT x VIN f OSC x L
I L , peak (Boost) =
Vendor Toko Toko Toko Murata Murata TDK TDK Coilcraft Coilcraft
Part No. DE2810C DE2810C MDT2520-CN LQM2HP-G0 LQM2HP-G0 CPL2512T CPL2512T LPS3010 LPS3010
where fOSC is the switching frequency (typically 2.5 MHz), and L is the inductor value in henries. A larger inductor value reduces the current ripple (and therefore peak inductor current), but is physically larger in size with increased dc resistance. Inductor values between 1 H and 1.5 H are usually suggested. The maximum inductor value to ensure stability is 2.0 H. For increased efficiency with the ADP2504, it is suggested a 1.5 H inductor be used. The inductor peak current is at the maximum in boost mode. To determine the actual maximum inductor current in boost mode, the input dc current should be estimated.
Output Capacitor Selection
The output capacitor selection determines the output voltage ripple, transient response and the loop dynamics of the ADP2503/ADP2504. The output voltage ripple for a given output capacitor is given by
VOUT , peak (Buck) = VOUT x (V IN - VOUT ) V IN x 8 x L x ( f OSC )2 x C OUT
VOUT , peak (Boost) =
I LOAD x (VOUT - V IN ) C OUT x VOUT x f OSC
V I IN ( MAX) = I LOAD( MAX) x OUT V IN
1
x

where is efficiency (assume 0.85 to 0.90). The saturation current rating of the inductor must be at least IIN(MAX) + ILOAD/2. Ceramic multilayer inductors can be used with lower current designs for a reduced overall solution size and dc resistance (DCR). These are available in low profile packages. Care must be taken as these derate quickly as the inductor value is increased especially at higher operating temperatures. Ferrite core inductors have good core loss characteristics as well as reasonable dc resistance. A shielded ferrite inductor reduces the EMI generated by the inductor.
Table 5. Recommended Output Capacitors
Vendor Murata TDK Murata TDK TDK Murata Value 2 x 10 F, 6.3 V 2 x 10 F, 6.3 V 22 F, 6.3 V 22 F, 6.3 V 22 F, 10 V 10 F, 10 V Part No. GRM188R60J106ME47 C1608JB0J106K GRM21BR60J226ME39 C2012X5R0J226M C3216X5R1A226K GRM21BR71A106KE51L
If the ADP2503/ADP2504 are operating in buck mode, the worst-case voltage ripple occurs for the highest input voltage, VIN. If the ADP2503/ADP2504 are operating in boost mode, the worst-case voltage ripple occurs for the lowest input voltage, VIN. The maximum voltage overshoot, or undershoot is inversely proportional to the value of the output capacitor. To ensure stability and excellent transient response, it is recommended to use a minimum of 22 F X5R 6.3 V or 2 x 10 F X5R 6.3 V capacitors at the output. The effective capacitance (includes temperature, dc bias effects) needed for stability is 14 F.
Dimensions L x W x H (mm) 1.6 x 0.8 x 0.8 (2) 1.6 x 0.8 x 0.8 (2) 2 x 1.25 x 1.25 2 x 1.25 x 1.25 2 x 1.25 x 1.25 2 x 1.25 x 1.25 (2)
Rev. PrB | Page 12 of 16
Preliminary Technical Data
Input Capacitor Selection
The ADP2503/ADP2504 require an input capacitor to filter noise on the VIN pin, and provide the transient currents while maintaining constant input and output voltage. A 10 F X5R/ X7R ceramic capacitor rated for 6.3 V is the minimum recom mended input capacitor. Increased input capacitance reduces the amplitude of the switching frequency ripple on the battery. Because of the dc bias characteristics of ceramic capacitors, a 0603, 6.3 V X5R/X7R, 10 F ceramic capacitor is preferable.
ADP2503/ADP2504
Table 6. Recommended Input Capacitors
Dimensions LxWxH (mm) 1.6 x 0.8 x 0.8 1.6 x 0.8 x 0.8
Vendor Murata TDK
Value 10 F, 6.3 V 10 F, 6.3 V
Part No. GRM188R60J106ME47 C1608JB0J106K
Rev. PrB | Page 13 of 16
ADP2503/ADP2504 PCB LAYOUT GUIDELINES
Poor layout can affect ADP2503/ADP2504 performance, causing electromagnetic interference (EMI) and electromagnetic compatibility (EMC) performance, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following rules:
* * * *
Preliminary Technical Data
Route the output voltage path away from the inductor and SW node to minimize noise and magnetic interference. Maximize the size of ground metal on the component side to help with thermal dissipation. Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes.
Place the inductor, input capacitor, and output capacitor close to the IC using short tracks. These components carry high switching frequencies and large tracks act like antennas.
ADP2503/ADP2504 EVALUATION BOARD
VIN J1 8mm C1
10mm L1 J3 C2 C3 JP1 JP1
VOUT
U1 R3 PGND J2 C4
PGND J4
TP2
TP1
R2 J6 1 EN
R1 J5 1 SYNC
07475-026
Figure 28. ADP2503/ADP2504 Evaluation Board
Rev. PrB | Page 14 of 16
Preliminary Technical Data OUTLINE DIMENSIONS
3.00 BSC SQ 0.30 0.23 0.18
6 10 *EXPOSED PAD (BOTTOM VIEW)
ADP2503/ADP2504
0.50 BSC
PIN 1 INDEX AREA 0.50 0.40 0.30
TOP VIEW
1.74 1.64 1.49
5
1
0.80 0.75 0.70 SEATING PLANE
0.80 MAX 0.55 NOM
2.48 2.38 2.23 0.05 MAX 0.02 NOM
PIN 1 INDICATOR (R 0.20)
*PADDLE CONNECTED TO GND.
Figure 298. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm x 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model ADP2503ACPZ-2.8-R71 ADP2503ACPZ-3.3-R71 ADP2503ACPZ-3.5-R71 ADP2503ACPZ-4.2-R71 ADP2503ACPZ-4.5-R71 ADP2503ACPZ-5.0-R71 ADP2504ACPZ-2.8-R71 ADP2504ACPZ-3.3-R71 ADP2504ACPZ-3.5-R71 ADP2504ACPZ-4.2-R71 ADP2504ACPZ-4.5-R71 ADP2504ACPZ-5.0-R71
1
Voltage 2.8 V 3.3 V 3.5 V 4.2 V 4.5 V 5.0 V 2.8 V 3.3 V 3.5 V 4.2 V 4.5 V 5.0 V
Maximum Current 0.6 A 0.6 A 0.6 A 0.6 A 0.6 A 0.6 A 1A 1A 1A 1A 1A 1A
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
060408-B
0.20 REF
Package Description 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
Package Option CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9 CP-10-9
Branding L9Y L9Z LAP LA0 LA1 LA2 L9T L85 LAN L9U L9V L9W
Z = RoHS Compliant Part.
Rev. PrB | Page 15 of 16
ADP2503/ADP2504 NOTES
Preliminary Technical Data
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07475-0-8/08(PrB)
Rev. PrB | Page 16 of 16

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